The invention relates to a method of providing a vertical interconnect between a first and a second thin-film microelectronic device.
The invention further relates to an integrated circuit.
If a plurality of thin-film microelectronic devices, for example a plurality of field-effect transistors, is to constitute an IC, interconnects between these devices are to be provided. An interconnect provides an electrical connection between a terminal of a first and a second thin-film microelectronic device. Sometimes, it is necessary to provide an interconnect which extends through a stack of layers. An interconnect of this type is referred to as a vertical interconnect or, in short, a via.
In silicon-based IC technology, a vertical interconnect is made by photolithographically defining a contact window, etching so as to obtain a contact hole and, subsequently, filling the contact hole by depositing metal (see e.g. VLSI Technology, ed. Sze, McGraw-Hill (1983), p 447).
In the field of microelectronics based on devices consisting substantially of organic materials, such devices being disclosed, for example, by Garnier et al. in Science, vol. 265 (1994), pp. 1684-1686, a method of providing a vertical interconnect between thin film devices, let alone a method less elaborate than the method mentioned hereinabove, is not known. Microelectronics based on organic materials may be effectively used in those applications where the use of silicon-based technology is prohibitively expensive.
It is an objective of the invention, inter alia, to provide a method of providing a vertical interconnect between a first and a second thin-film device, in particular between devices consisting substantially of organic materials. The method is to be simple and reliable.
This objective is achieved by a method of providing a vertical interconnect between a first and a second thin-film microelectronic device, said method comprising the steps of:
providing a vertical interconnect area,
said vertical interconnect area being an area of overlap of a stack of a first organic electrically conducting area, an organic electrically insulating area and a second organic electrically conducting area,
said first organic electrically conducting area being electrically connected to a terminal of said first microelectronic device,
said second organic electrically conducting area being electrically connected to a terminal of said second microelectronic device, and
notching the vertical interconnect area using a tool tip, thereby forming the vertical interconnect.
Although the details as to how and why the method works are unclear, the method is found to be simple and very reliable. Typically, it is possible to make 118 vias, each via having a contact resistance of 3 kxcexa9 on average, in a single run without a single failure. The method does not involve any photolithographic step, which makes it less elaborate than methods known from silicon-based IC technology. Notching does not require a large force.
The method appears to be effective, substantially irrespective of the material properties of the organic materials used. In particular, the method appears still effective if the insulating area is far less deformable than both the first and second electrically conducting areas, as is the case if a layer of cross-linked polyvinylphenol is disposed between layers of a conducting polyaniline.
It is indeed surprising that the method is effective in providing a vertical interconnect. After all, one would expect that the presence of a notch implies the absence of (electrically conducting) matter, whereas the presence of a vertical interconnect requires the presence of electrically conducting matter.
It has been found that the choice of the insulating material for the manufacture of the insulating area is not critical. Examples include organic electrically insulating materials known per se. Good results have been obtained with a polyvinylalcohol or a polyvinylphenol.
The choice of the organic electrically conducting material used to form the first and second electrically conducting areas is not critical either. Suitable examples include heavily doped semiconducting polymers (oligomers) known per se, such as a polynaniline, a polythiophene, a polypyrrole, a polyphenylene, a polyphenylenevinylene, or, in particular, a poly-3,4-ethylenedioxythiophene.
For the supporting substrate use can suitably be made of synthetic resins, such as a polyamide. Glass and silica substrates can also be suitably used.
A suitable surface area of the vertical interconnect area is, for example, 20 xcexcm by 20 xcexcm. Smaller surface areas, such as 100 xcexcm2, are also possible.
A suitable thickness of the stack constituting the vertical interconnect area is 2 xcexcm or less. A larger thickness, such as 5 xcexcm or 20 xcexcm, is possible but leads to an increase of the force needed to drive in the tool tip. Notching is less accurate if a larger force is applied.
Notching the vertical interconnect area involves positioning the tool tip opposite the vertical interconnect area, driving in the tool tip and retracting the tool tip from the vertical interconnect area.
As a result of the presence of the notch, the contact resistance of the vertical interconnect area drops dramatically, i.e, a vertical interconnect is formed.
The extent of notching required in order to form a vertical interconnect can be determined by a simple empirical procedure, in which, for example, the force used to drive in the tool tip is varied.
The actual shape of the notch, for example its diameter at the top or the extent to which it is driven in, depends on many parameters, such as the amount of force applied to the tool tip, the angle of attack of the tool tip, the shape of the tool tip and the nature of the supporting surface. For example, if the tool tip is needle-shaped and attacks the via (the term via is short for both vertical interconnect and vertical interconnect area) at substantially a right angle, the notch is shaped like a crater. If lateral movement of the tool tip occurs during notching, the notch takes the form of a trench or a set of scratches.
By simply expanding the stack comprising the vertical interconnect area with further electrically conducting areas and/or further insulating areas, the method can be used to provide multilevel vertical interconnects.
It is noted that in an English-language abstract of the Japanese Patent Application JP-A-5-299514, a method of providing a via using a tool tip is disclosed. It is not apparent from said document that the known method relates to a method of providing a via between thin-film microelectronic devices, let alone thin-film microelectronic devices consisting substantially of organic materials. Furthermore, the obtuse tool tip does not notch the vertical interconnect area but is used as a pressing member for pressing the conducting tracks against each other. Pressing requires large forces.
In order to minimize the pressure exerted on areas outside the via, which may lead to undesirable (permanent) deformation of said areas, an attack at a more or less right angle from horizontal is preferred.
In order to reduce the force needed to drive in the tool tip, a tapered tool tip is preferred. In order to avoid excessive pressure being exerted on areas outside the via, the tapered section is preferably longer than the thickness of the via and should have an included angle which is acute or, preferably, less than 20 degrees.
The tool tip may be wedge-shaped or needle-shaped. Probe tips used for probing circuits on silicon chips are particularly effective. Such probe tips are durable, available in many varieties and have a well-defined geometry.
In order to reduce wear, hard and wear-resistant tool tips, such as tungsten carbide tool tips, may be used.
A preferred embodiment of the method in accordance with the invention is characterized in that a tapered tool tip is used having a tip radius between 0.1 xcexcm and 5.0 xcexcm.
Although tool tips with a tip radius of 10 xcexcm, 25 xcexcm or 50 xcexcm have been used successfully, tool tips having a tip radius smaller than 5.0 xcexcm are found to be more reliable. Tool tips smaller than 0.1 xcexcm break easily. The tip radius is defined as the radius of curvature at the point of the tip.
In another preferred embodiment of the method in accordance with the invention, the first and second organic electrically conducting areas comprise an electrically conducting polyaniline. By using electrically conducting polyaniline, the conductivity of which typically is 10 to 100 S/cm, a via having a contact resistance as low as 3 kxcexa9 can be made. For many applications, this resistance is sufficiently small. For example, if the via interconnects field-effect transistors consisting substantially of organic materials, the current flowing through the via will typically be in the order of 10xe2x88x929 to 10xe2x88x926 A. Given a resistance of 3 kxcexa9, the resulting voltage drop across the via is negligible.
Notching may be performed manually using a hand-held tool, but if many, for example more than 30, vias are to be made, notching is preferably done using mechanized (automated) equipment. At least in the case of small series or one-off applications, probe stations used to test circuits on silicon chips are convenient.
Many vias can be made simply one after the other. Throughput can be increased, however, if the method is modified in that a tool comprising a plurality of tool tips is used, thus allowing a plurality of vias to be made simultaneously. An example of such a tool is a metal plate etched in accordance with a desired pattern so as to obtain a plurality of pins. It is to be noted that the force required to notch the vias is apparently proportional to the number of vias to be made simultaneously.
The method is to provide a vertical interconnect between a first and a second thin-film microelectronic device. Obviously, this can only be done if the first and second electrically conducting areas of the vertical interconnect area are connected, respectively, to the first and second thin-film microelectronic device. Although the method can be suitably used in conjunction with any type of organic thin-film microelectronic device, the method is particularly effective in forming a vertical interconnect between field-effect transistors consisting substantially of organic materials.
The method in accordance with the invention is sufficiently reliable so as to allow integrated circuits to be made using said method.
The invention therefore further relates to an integrated circuit which, in accordance with the invention, is characterized in that the integrated circuit comprises at least one vertical interconnect obtainable by the method in accordance with the invention.
In a preferred embodiment, the integrated circuit substantially consists of organic materials. As a result of the low cost of organic materials and their ease of processing, an integrated circuit consisting substantially of organic materials, in short an organic IC, can be manufactured at a much lower cost than a silicon-based IC.
In a particularly preferred embodiment, the thin-film devices are part of the stack of layers used to form the vertical interconnect area. In this case, a stack comprising only four layers, two of which are patterned, is sufficient to provide an IC.
A thin-film microelectronic device which may be conveniently accommodated by such a four-layered stack is a field-effect transistor.
Examples of circuits which can be successfully implemented in this manner include logic gates, such as an invertor, a NAND gate, a NOR gate, and an AND gate as well as combinations thereof, such as flip flops, frequency dividers and ring oscillators.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.